It has been known to employ bipolar transistors for reading/wiring circuits and digit line select circuits, in order to increase the operation speed of CMOS static RAMs. For example, such an arrangement has been disclosed in Japanese Patent Laid-Open No. 58193/1981.
In such a semiconductor memory device, since an operation (bias) current is supplied at all times to the bipolar transistor, the current consumed becomes a very large value. Therefore, there arises a serious defect directed in that it is impractical to have a battery back-up operation, even though a great merit of a CMOS static RAM is the fact that such a battery back-up operation is generally available. In the reading circuit, furthermore, a bipolar transistor is used as a column switching circuit, and a current is supplied to a memory cell that is selected via the column switching circuit to obtain a reading signal. However, the value of reading current cannot be increased since it is determined by the conductance of MOSFET in the memory cell. This is because, although the element size must be increased to increase the reading current, it is not allowed to increase the element size of the momory cells from the standpoint of increasing the memory capacity. Therefore, despite the fact that the bipolar transistors are employed, the reading speed of the above-mentioned conventional semiconductor memory device cannot be so increased. Further, since the column switching circuit is constituted by the bipolar transistors, it becomes difficult to set the level (select/non-select levels) of output signals of the column address decoder circuit.